SUNNYVALE, Calif., June 18, 2018 (GLOBE NEWSWIRE) — Real Intent, Inc., a leading provider of SoC and FPGA sign-off verification solutions, today announced Verix PhyCDC – a new tool to debug clock domain crossing violations at the gate level netlist of digital designs. Complementing Real Intent’s Verix CDC solution for RTL sign-off, Verix PhyCDC maintains Real Intent’s product leadership in delivering the industry’s fastest-performance, highest-capacity and most precise CDC solutions in the market.
Verix PhyCDC targets the post-synthesis stage of SoC design at the gate level, where physical implementation tools can introduce changes that might cause unintended signal noise and functional failures. It leverages the results from RTL CDC to identify incremental CDC paths and constraints to optimize the CDC analysis at gate level while providing maximum coverage. Verix PhyCDC addresses malfunctions such as glitching on control signals, clock networks and data signal paths; and incorrect optimization of clock synchronizer logic. Verix PhyCDC also includes iDebug, Real Intent’s state-of-the-art design intent debugger and data manager.
Ramesh Dewangan, vice president of product strategy at Real Intent, said, “CDC verification traditionally has been targeted at RTL sign-off before physical implementation begins. The CDC problems introduced during synthesis along with the addition of test logic and low-power optimizations are risk factors for SoC designs at the physical implementation stage. With the largest capacity of any tool in the industry, Verix PhyCDC provides verification without sacrificing precision. Its easy setup by reusing constraints from RTL, parallel processing to significantly reduce runtime, and incremental sign-off through diff analysis gives implementation teams the fastest pathway for RTL + Netlist CDC sign-off. They can be confident the designs they are handing off to tape-out are free of CDC bugs.”
Real Intent will give presentations on Verix PhyCDC in Booth #1431 during the Design Automation Conference in San Francisco, June 25 to 27. Appointment times can be arranged here.
Verix PhyCDC is available now. Pricing depends on product configuration. For more information, please email email@example.com
About Real Intent
Real Intent is the industry leader in static sign-off of digital designs. Companies worldwide rely on Real Intent’s EDA software to accelerate early functional verification and sign-off at RTL as well as gate-level. Its intent-driven static technology powers solutions for clock and reset domain crossing analysis (CDC, RDC), and cleaned RTL code and X-pessimism correction, to ensure design success for SoCs and FPGAs. Real Intent products lead the market in performance, capacity and accuracy, and provide a faster time to tape out. Please visit www.realintent.com for more information.
Verix, Ascent, and Meridian are trademarks of Real Intent, Inc. All other trademarks and trade names are the property of their respective owners.
Barbara Benjamin for Real Intent
CDC: Clock Domain Crossing
EDA: Electronic Design Automation
FPGA: Field-Programmable Gate Array
RTL: Register Transfer Level
A photo accompanying this announcement is available at http://www.globenewswire.com/NewsRoom/AttachmentNg/b86d9764-026b-4ae3-8d31-be8f80590ede